1. Field of the Invention
This invention relates to the transmission of data and, more particularly, to receivers that receive transmitted differential pairs of signals that selectively shift downward in voltage depending on the common mode voltage of those differential signals.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
The transmission of data involves sending and receiving data over a transmission path. The transmission path is connected between a pair of transceivers and each transceiver can have a receiver and a transmitter. The receiver receives data from the transmission path and the transmitter drives data onto the transmission path.
Numerous transmission protocols have been established for sending and receiving data across a transmission path. For example, IEEE Std. 1596 specifies a protocol for sending differential signals across a transmission path in order to achieve a relatively high transfer rate (e.g., 16 bits can be transferred every 2 ns). IEEE Std. 1596 utilizes low voltage differential signals (LVDS) which are, in some instances, as low as 250 mV swing compatible with low voltage MOS, BiCMOS, Bipolar, and GaAs transceiver circuitry. Ideally, the power dissipation of LVDS transceivers or the LVDS input/output (I/O) interface devices is low since only approximately 2.5 mA is needed to generate the differential voltage across a nominal 100 ohm termination resistor.
The receiver or buffer of a LVDS I/O interface device essentially operates as a differential sense amplifier that can ideally accept a relatively wide common-mode input voltage range with a high common-mode rejection ratio. However, as with most circuits, a practical sense amplifier has a limit as to the common-mode voltage that it can accept. Most conventional sense amplifiers are rated based on the common-mode voltage range that they can accept and still remain operational. Thus, many sense amplifiers are rated as either accepting of a relatively high common-mode voltage range or a relatively low common-mode voltage range.
The maximum voltage of the differential inputs acceptable to a LVDS receiver can be approximately 2.4 volts, with a minimum voltage of approximately 0 volts. At somewhat low differential swings, a LVDS receiver might then be rated as one that receives both a high and a low common-mode voltage. In order to achieve this relatively wide common-mode range, many conventional receivers employ a multiple stage architecture. A first stage might be a pair of differential transistors connected to load resistors tuned to a high common-mode range, and the second stage might be another pair of differential transistors and load resistors tuned to a relatively low common mode range. The multiple stages must be connected to each differential input terminal, with the parallel pair of stages then merged to achieve a single ended signal that will conform to the minimal accepted levels of the circuit fed by the receiver. Various examples of multi-stage, parallel sense architecture, and the complex nature of such circuitry is set out in U.S. Pat. Nos. 4,907,121 and 6,236,242 (herein incorporated by reference).
Instead of using multiple stage sense circuits, it would be desirable to implement only a single stage to achieve sensing across the entire common-mode range. Use of a single sense circuit can be achieved if, for example, the common-mode range is slightly reduced or narrowed. In many differential signal protocols, a common mode range need not extend from approximately 0 volts to 2.4 volts. Instead, the common-mode range might simply be, for example, from 0.8 volts to 2.4 volts, thereby desirably allowing a single sense circuit. Unfortunately, differential signals at the upper end of the common mode specification require a power supply that exceeds those signals.
In addition to employing a single sense circuit, it would be of further benefit to reduce the power consumption within the overall receiver by introducing a power supply voltage that is less than the maximum single-ended voltage of a differential pair of voltages (hereinafter xe2x80x9cmaximum voltage on a differential pairxe2x80x9d), and less than the maximum common-mode input voltage. The improved receiver can, therefore, detect the differential voltage change using a rather simple, low voltage sense circuit, even though the common-mode input voltage might exceed the power supply of the sense circuit or receiver.
The problems outlined above are in large part solved by an improved transmission system. The transmission system includes a receiver that provides many advantages over conventional receivers. For example, the receiver uses a simple sense circuit made up of only one stage and avoids the complexities of the multi-stage, parallel-fed sense architecture. The sense circuit can simply have a pair of differential transistors connected to respective resistor loads. Multiple pairs of differential transistors and load resistors can, therefore, be avoided and the costs associated therewith. Second, the sense circuit can sense the full extent of a somewhat reduced (yet still relatively wide) common-mode input voltage range.
According to one example, the minimum and maximum voltages on a differential pair can range from 800 millivolts to 2.4 volts. If the differential swing is only 100 millivolts, then the sense circuit can sense across a common mode range of approximately 850 millivolts to 2.35 volts. Like other circuitry within the buffer (or receiver), the sense circuitry operates at a reduced power supply voltage that need not be equal to or greater than the maximum voltage being received by the receiver or sensed by the sense circuitry. Instead, the receiver employs a level shift circuit that selectively reduces each voltage of the differential input signal (i.e., the common-mode input voltage) so that the maximum voltage of the differential pair of signals can exceed the power supply voltage. The amount by which the maximum differential input voltage (alternatively known as the maximum voltage on the differential pair) can exceed the supply voltage is predetermined and, preferably, can be in the range of 150 millivolts to 250 millivolts and, more preferably, between 175 millivolts to 225 millivolts.
The level shift circuit reduces each voltage of the differential input voltages only if the common-mode voltage of the differential input voltages exceeds a certain threshold. According to one example, the amount by which the level shift circuit reduces each voltage can be somewhere in the range of 350 millivolts to 450 millivolts and, more preferably, between 375 millivolts to 425 millivolts. If the maximum voltage of the differential input signals is 2.4 volts as received upon the termination resistor, the level shift circuit employs a transistor that selectively forwards current through a reducing resistor so that the common mode voltage of differential signals having a high common mode voltages is reduced. For example, the amount of reduction can be approximately 400 millivolts to level shift the 2.4 volt input to approximately 2.0 volts as received upon the sense circuit. If the sense circuit is powered by a 1.8 volt power supply, for example, then the 2.0 volt input will provide enough margin so that a differential of, for example, 100 millivolts can be registered on the output of the sense circuit with minimal attenuation.
The level shift circuit is designed to only level shift differential input signals that have a relatively high common-mode voltage. If the differential signals have a relatively low common-mode voltage (e.g., lower than 800 millivolts, or between 800 millivolts to 1.0 volts), then the level shift circuit does not downward shift the common mode voltage. This proves beneficial since any downward shifting of the lower end of the common mode range would force a more complex sense circuit, possibly necessitating dual-stage parallel-fed sense circuits where multiple pairs of differential transistors and load resistors would be needed. Instead, the level shift circuit adapts and is controlled by the common-mode voltage to only level shift the high common-mode voltages that exceed 1.0 volts or, possibly, 1.5 volts.
A common mode range between 800 millivolts and 2.4 volts is utilized and can be specified within, for example, the transceiver or I/O interface circuits of communication modules described by the Optical Internetworking Forum (xe2x80x9cOIFxe2x80x9d), as set out in the System Packet/Fiber Interface (xe2x80x9cSFIxe2x80x9d) protocol. Differential signals sent across an SFI-4 transmission path between, for example, a framer/mapper and a serializer/deserializer (SERDES) can, therefore, have a specified minimum and maximum differential signal range of 800 millivolts to 2.4 millivolts (with a common mode range somewhere therebetween depending on the swing of the differential signals). Utilizing this range in a simple sense circuit that is a low power sense circuit within a low power receiver proves advantageous over conventional transceivers that operate according to the SFI-4 protocol of an OC-192 SERDES framer interface, for example.
According to one embodiment, a transmission system is provided. The transmission system includes a transmitter (i.e., a driver) and a receiver (or buffer) connected by a transmission path. The transmission path includes a pair of transmission lines across which a pair of differential signals are sent. The receiver receives the pair of differential signals and includes a detect circuit, a level shift circuit, and a sense circuit. The detect circuit detects the voltages upon the pair of differential signals and, more particularly, the common mode voltage of those signals. If the common mode voltage exceeds a predefined amount, then the detect circuit will send a control signal to the level shift circuit. The level shift circuit, upon receiving the control signal, reduces each voltage of the differential input signal. Preferably, the level shift circuit reduces the voltage by forwarding a selectable current through a resistor that causes the IR drop to register a lessened or reduced voltage on the input of the sense circuit. The sense circuit will then receive the reduced voltage on each of the differential input signals.
The detect circuit is, therefore, used to detect if a common mode voltage of the differential signals exceeds a threshold value. The level shift circuit reduces each voltage of the differential input signal, or the common mode voltage of those differential signals, if the common mode voltage being detected exceeds the threshold amount. The level shift circuit simply contains a pair of resistors where one end of each of the pair of resistors is connected to the differential input line, and the other end of each of the pair of resistors is connected to a corresponding one of the pair of transistors. The pair of transistors control the amount of voltage reduction (if any) adaptively placed onto the sense circuit. The sense circuit is preferably a pair of differential transistors connected to a pair of load resistors.
According to yet another embodiment, a method is provided. The method includes the steps of reducing the voltages of the differential input signals if a common-mode voltage of the differential input signals exceed a predefined amount. The voltages of the differential input signals are not reduced if the common-mode voltage of the differential input signals does not exceed a predefined amount. The reduced or non-reduced differential input signals are then forwarded to the sense circuit that produces signal levels that conform to the minimal accepted levels of the receiving system.